Achievements

After a month of community website voting, the organizers of the 2017 Intel Innovative FPGA contest announced the semi-finalists of the Asia-Pacific-Japan region. One hundred projects were submitted by the group. Two outstanding projects originating in the DTU Faculty of Electrical Engineering earned them a place in the regional semi-finals. The projects were entitled “A Drowsiness Warning System Using FPGA”, by Nguyen The Duc and Ho Van Chuong, and “An image processing application in car lane identification, using the Hough transform algorithm”, by Le Minh Hai and Truong Quoc Dung.

Organized by the Intel Corporation and Terasic in the US, the international 2017 Intel Innovate FPGA specializes in embedded system design. Students, engineers, lecturers and companies involved in the production of embedded systems compete to exhibit their design skills in the contest, which began in December 2017 and is divided into four regions: the Americas, Europe-Middle East-Africa, Greater China and Asia-Pacific-Japan. Teams winning regional first, second and third prizes will receive certificates and money prizes, in addition to trips to the US to compete in the world finals.

  

Using machine learning with image processing technology and some algorithms, SVM in the case of the first project and the Hough algorithm in the second, the DTU Faculty of Electrical Engineering planned systems that would make driving safer and legal. In the first project, a camera focuses on the driver’s face to detect signs of fatigue and sounds a warning if it does so. Furthermore, statistics on the driver’s condition are collected and stored to forecast the probability of further drowsiness and then emit an early-warning alarm. In the second project, a camera is installed at the front of the vehicle to detect highway lanes and traffic conditions. Whenever the driver moves into the wrong lane, the system sounds a warning for the driver to change direction and drive more safely and lawfully.

“We have just two months to continue the development on our projects using the Terasic DE10-Nano tools provided by the organizers,” explained Le Minh Hai of K20ETS, a member of the group working on the second project. “In addition to the design files, which include items such as ‘a system feature description’, ‘design methods’ and ‘system performance objectives’, we are also producing a demo video to send to the selection committee. The contest this year has many entrants, including engineers from embedded systems companies, so is highly competitive. We know that, with the dedicated support and guidance of our lecturers, we will do our best to succeed.”